B.TECH 6TH SEMESTER (ELECTRONICS AND COMMUNICATION ENGINEERING)












Unit 1








             VLSI   DESIGN







Introduction to VLSI




















Manufacturing process of CMOS integrated circuits







CMOS n-well process design rules









Packaging integrated circuits







Trends in process technology







MOS transistor







Energy band diagram of MOS system







MOS under external bias







derivation of threshold voltage equation







Secondary effects in MOSFETS




Unit 2



MOSFET scaling and small geometry effects







MOScapacitances







Modeling of MOS transistors using SPICE







Capacitance models







The Wire: Interconnect parameters: capacitance







Resistanceand inductance







Electrical wire models: The ideal wire







The lumpedmodel







The lumped RC model







The distributed RC model







The transmission line model








SPICE wire models




Unit 3




MOS inverters








Resistive load inverter







Inverter with n-type MOSFET load







CMOS inverter: Switching Threshold







Noise Margin







Dynamic behavior of CMOS inverter







Computing capacitances







Propagation delay







Dynamic and Static  power consumption







Energy and energy delay product calculations







Stick diagram







IC layout design and tools



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B.TECH ( COMPUTER SCIENCE ENGINEERING )

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